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| rom type mask rom mask rom one time prom package 20p2e/f-a 20p2e/f-a 20p2e/f-a ram size ( 4 bits) 48 words 64 words 64 words pin configuration (top view) rom (prom) size ( 9 bits) 1024 words 2048 words 2048 words product m34282m1-xxxgp * m34282m2-xxxgp * m34282e2gp * description the 4282 group enables fabrication of 8 7 key matrix and has the followin timers; ? an 8-bit timer which can be used to set each carrier wave and has two reload register ? an 8-bit timer which can be used to auto-control and has a reload register. features number of basic instructions ............................................. 68 minimum instruction execution time ............................ 8.0 s (at f(x in ) = 4.0 mhz, system clock = f(x in )/8) supply voltage ................................................. 1.8 v to 3.6 v subroutine nesting ..................................................... 4 levels timer timer 1 ................................................................... 8-bit timer (this has a reload register and carrier wave output auto-control function) timer 2 ................................................................... 8-bit timer (this has two reload registers and carrier wave output function) logic operation function (xor, or, and) ram back-up function key-on wakeup function (ports d 4 ? 7 , e 0 ? 2 , g 0 ? 3 ) .... 11 i/o port (ports d, e, g, carr) .......................................... 16 oscillation circuit ..................................... ceramic resonance watchdog timer power-on reset circuit voltage drop detection circuit ......................... typical:1.50 v (system reset) application various remote control transmitters 4282 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers v s s 2 3 4 5 6 7 8 9 10 1 1 9 18 17 1 6 15 1 4 1 3 1 2 1 1 20 d 7 d 2 d 3 d 4 d 5 d 1 d 0 carr v dd d 6 e 2 g 3 g 2 e 0 e 1 x in x o u t g 0 g 1 m 3 4 2 8 2 m x - x x x g p preliminar y notice: this is not a final specification. some parametric limits are subject to change. * : under development (june, 2000) outline 20p2e/f-a
mitsubishi electric 2 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. block diagram r a m ( 4 8 , 6 4 w o r d s ? 4 b i t s ) r o m ( 1 0 2 4 , 2 0 4 8 w o r d s ? 9 b i t s ) 7 2 0 s e r i e s c p u c o r e m e m o r y i / o p o r t i n t e r n a l p e r i p h e r a l f u n c t i o n t i m e r / r e m o t e - c o n t r o l c a r r i e r - w a v e o u t p u t t i m e r 1 ( 8 b i t s , c a r r i e r w a v e o u t p u t c o n t r o l ) t i m e r 2 ( 8 b i t s , c a r r i e r w a v e g e n e r a t i o n ) s y s t e m c l o c k g e n e r a t i o n c i r c u i t x i n - x o u t ( n o t e ) r e g i s t e r b ( 4 b i t s ) r e g i s t e r a ( 4 b i t s ) r e g i s t e r d ( 3 b i t s ) r e g i s t e r e ( 8 b i t s ) s t a c k r e g i s t e r s k ( 4 l e v e l s ) a l u ( 4 b i t s ) p o r t d 4 p o r t g 4 p o r t e 2 4 1 w a t c h d o g t i m e r ( 1 4 b i t s ) r e s e t ( v o l t a g e d r o p d e t e c t i o n c i r c u i t ) n o t e : p r o m 2 0 4 8 w o r d s ? 9 b i t s , r a m 6 4 w o r d s ? 4 b i t s f o r b u i l t - i n p r o m v e r s i o n . mitsubishi electric 3 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. performance overview function 68 8.0 s (f(x in ) = 4.0 mhz, system clock = f(x in )/8, v dd = 3 v) 2048 words ? 9 bits 1024 words ? 9 bits 64 words ? 4 bits 48 words ? 4 bits four independent output ports four independent i/o ports with the pull-down function 3-bit input port with the pull-down function 2-bit output port (e 0 , e 1 ) 4-bit i/o port with the pull-down function 1-bit output port; cmos output 8-bit timer with a reload register 8-bit timer with two reload registers 4 levels (however, only 3 levels can be used when the tabp p instruction is executed) cmos silicon gate 20-pin plastic molded ssop (20p2e/f-a) 20 c to 85 c 1.8 v to 3.6 v 400 a (f(x in ) = 4.0 mhz, system clock = f(x in )/8, v dd = 3 v) 0.1 a (at room temperature, v dd = 3 v) parameter number of basic instructions minimum instruction execution time memory sizes input/output ports timer subroutine nesting device structure package operating temperature range supply voltage power dissipation (typical value) rom ram d 0 d 3 d 4 d 7 e 0 e 2 e 0 , e 1 g 0 g 3 carr timer 1 timer 2 active mode ram back-up mode m34282m2/e2 m34282m1 m34282m2/e2 m34282m1 output i/o input output i/o output pin description name power supply ground system clock input system clock output output port d i/o port d i/o port e i/o port g carrier wave output for remote control input/output input output output i/o output input i/o output function connected to a plus power supply. connected to a 0 v power supply. i/o pins of the system clock generating circuit. connect a ceramic resonator between pins x in and x out . the feedback resistor is built-in between pins x in and x out . each pin of port d has an independent 1-bit wide output function. the output structure is p-channel open-drain. 1-bit i/o port. for input use, set the latch of the specified bit to 0. when the built- in pull-down transistor is turned on, the key-on wakeup function using h level sense and the pull-down transistor become valid. the output structure is p-channel open-drain. 2-bit (e 0 , e 1 ) output port. the output structure is p-channel open-drain. 3-bit input port. for input use (e 0 , e 1 ), set the latch of the specified bit to 0. when the built-in pull-down transistor is turned on, the key-on wakeup function using h level sense and the pull-down transistor become valid. port e 2 has an input-only port and has a key-on wakeup function using h level sense and pull- down transistor. 4-bit i/o port. for input use, set the latch of the specified bit to 0. the output structure is p-channel open-drain. when the built-in pull-down transistor is turned on, the key- on wakeup function using h level sense and pull-down transistor become valid. carrier wave output pin for remote control. the output structure is cmos circuit. pin v dd v ss x in x out d 0 d 3 d 4 d 7 e 0 e 2 g 0 g 3 carr mitsubishi electric 4 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. connections of unused pins pin d 0 d 7 e 0 , e 1 e 2 g 0 g 3 connection open or connect to v dd pin (note 1). set the output latch to 1 and open, or connect to v dd pin (note 2). open or connect to v ss pin. set the output latch to 1 and open, or connect to v dd pin (note 2). notes 1: ports d 4 d 7 : set the bit 2 (pu0 2 ) of the pull-down control register pu1 to 0 by software and turn the pull-down transistor off. 2: set the corresponding bits of the pull-down control register pu0 to 0 by software and turn the pull-down transistor off. (note in order to set the output latch to 1 to make pins open) after system is released from reset, a port is in a high-impedance state until the output latch of the port is set to 1 by software. accordingly, the voltage level of pins is undefined and the excess of the supply current may occur. to set the output latch periodically is recommended because the value of output latch may change by noise or a program run away (caused by noise). (note when connecting to v ss and v dd ) connect the unused pins to v ss or v dd at the shortest distance and use the thick wire against noise. port function control bits 1 bit output: 2 bits input: 3 bits 4 bits 1 bit control instructions sd rd cld sd rd cld szd oea iae iae oga iag scar rcar control registers pu1 pu0 pu0 output structure p-channel open-drain p-channel open-drain p-channel open-drain cmos input/ output output (4) i/o (4) i/o (2) input (1) i/o (4) output (1) remark pull-down function and key-on wakeup function (programmable) pull-down function and key-on wakeup function (programmable) pull-down function and key-on wakeup function (programmable) pin d 0 d 3 d 4 d 7 e 0 e 1 e 2 g 0 g 3 carr port port d port e port g port carr definition of clock and cycle system clock (stck) the system clock is the source clock for controlling this product. it can be selected as shown below whether to use the cck instruction. cck instruction when not using when using instruction clock f(x in )/32 f(x in )/4 system clock f(x in )/8 f(x in ) instruction clock (instck) the instruction clock is a signal derived by dividing the system clock by 4, and is the basic clock for controlling cpu. the one instruction clock cycle is equivalent to one machine cycle. machine cycle the machine cycle is the cycle required to execute the instruction. mitsubishi electric 5 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. port block diagrams cld instruction sd instruction rd instruction ports d 0 d 3 s r q decoder register y (note 1) port e 2 (note 5) key-on wakeup input iae instruction register a a 2 skip decision (szd instruction) cld instruction sd instruction rd instruction s r q decoder register y pu1 i pull-down transistor key-on wakeup (note 2) ports e 0 , e 1 (note 5) oea instruction register a a j a j d t q pu0 j key-on wakeup input iae instruction (note 3) (note 3) ports g 0 , g 1 (note 5) key-on wakeup input oga instruction iag instruction register a a j a j d t q (note 3) pu0 2 port carr (note 1) timer 1 underflow signal d t q r v1 0 carrier wave output control signal carry (to timer 1) v1 2 carryd (from timer 2) s r q scar instruction rcar instruction car flag pu0 3 key-on wakeup input oga instruction iag instruction register a a k a k d t q (note 1) (note 4) (note 1) ports d 4 d 7 (note 5) pull-down transistor (note 1) (note 1) (note 1) pull-down transistor pull-down transistor pull-down transistor ports g 2 , g 3 (note 5) notes 1: 2: i represents bits 0 to 3. 3: j represents bits 0, 1. 4: k represents bits 2, 3. 5: applied voltage must be less than vdd. this symbol represents a parasitic diode. mitsubishi electric 6 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 1 amc instruction execution example fig. 2 rar instruction execution example fig. 3 registers a, b and register e function block operations cpu (1) arithmetic logic unit (alu) the arithmetic logic unit alu performs 4-bit arithmetic such as 4-bit data addition, comparison, and bit manipulation. (2) register a and carry flag register a is a 4-bit register used for arithmetic, transfer, exchange, and i/o operation. carry flag cy is a 1-bit flag that is set to 1 when there is a carry with the amc instruction (figure 1). it is unchanged with both a n instruction and am instruction. the value of a 0 is stored in carry flag cy with the rar instruction (figure 2). carry flag cy can be set to 1 with the sc instruction and cleared to 0 with the rc instruction. (3) registers b and e register b is a 4-bit register used for temporary storage of 4- bit data, and for 8-bit data transfer together with register a. register e is an 8-bit register. it can be used for 8-bit data transfer with register b used as the high-order 4 bits and register a as the low-order 4 bits (figure 3). (4) register d register d is a 3-bit register. it is used to store a 7-bit rom address together with register a and is used as a pointer within the specified page when the tabp p, bla p, or bmla p instruction is executed (figure 4). fig. 4 tabp p instruction execution example (cy) (m(dp)) (a) addition alu mitsubishi electric 7 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 5 stack registers (sks) structure fig. 6 example of operation at subroutine call (5) most significant rom code reference enable flag (urs) urs flag controls whether to refer to the contents of the most significant 1 bit (bit 8) of rom code when executing the tabp p instruction. if urs flag is 0, the contents of the most significant 1 bit of rom code is not referred even when executing the tabp p instruction. however, if urs flag is 1, the contents of the most significant 1 bit of rom code is set to flag cy when executing the tabp p instruction (figure 4). urs flag is 0 after system is released from reset and returned from ram back-up mode. it can be set to 1 with the ursc instruction, but cannot be cleared to 0. (6) stack registers (sks) and stack pointer (sp) stack registers (sks) are used to temporarily store the contents of program counter (pc) just before branching until returning to the original routine when; performing a subroutine call, or executing the table reference instruction (tabp p). stack registers (sks) are four identical registers, so that subroutines can be nested up to 4 levels. however, one of stack registers is used when executing a table reference instruction. accordingly, be careful not to over the stack. the contents of registers sks are destroyed when 4 levels are exceeded. the register sk nesting level is pointed automatically by 2-bit stack pointer (sp). figure 5 shows the stack registers (sks) structure. figure 6 shows the example of operation at subroutine call. (7) skip flag skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. note : the 4282 group just invalidates the next instruction when a skip is performed. the contents of program counter is not increased by 2. accordingly, the number of cycles does not change even if skip is not performed. however, the cycle count becomes 1 if the tabp p, rt, or rts instruction is skipped. sk 0 sk 1 sk 2 sk 3 (sp) = 0 (sp) = 1 (sp) = 2 (sp) = 3 program counter (pc) executing rt instruction executing bm instruction stack pointer (sp) points 3 at reset or returning from ram back-up mode. it points 0 by executing the first bm instruction, and the contents of program counter is stored in sk 0 . when the bm instruction is executed after four stack registers are used ((sp) = 3), (sp) = 0 and the contents of sk 0 is destroyed. returning to the bm instruction execution address with the rt instruction, and the bm instruction is equivalent to the nop instruction. (sp) 0 (sk 0 ) 0001 16 (pc) sub1 main program 0002 16 nop address 0000 16 nop 0001 16 bm sub1 subroutine sub1 : nop rt (pc) (sk 0 ) (sp) 3 note: mitsubishi electric 8 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 7 program counter (pc) structure fig. 8 data pointer (dp) structure fig. 9 sd instruction execution example (8) program counter (pc) program counter (pc) is used to specify a rom address (page and address). it determines a sequence in which instructions stored in rom are read. it is a binary counter that increments the number of instruction bytes each time an instruction is executed. however, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (tabp p) is executed. program counter consists of pc h (most significant bit to bit 7) which specifies to a rom page and pc l (bits 6 to 0) which specifies an address within a page. after it reaches the last address (address 127) of a page, it specifies address 0 of the next page (figure 7). make sure that the pc h does not exceed after the last page of the built-in rom. (9) data pointer (dp) data pointer (dp) is used to specify a ram address and consists of registers x and y. register x specifies a file and register y specifies a ram digit (figure 8). register y is also used to specify the port d bit position. when using port d, set the port d bit position to register y certainly and execute the sd, rd, or szd instruction (figure 9). p 3 p 2 p 1 p 0 a 6 a 5 a 4 a 3 a 2 a 1 a 0 program counter (pc) pc h specifying page pc l specifying address x 1 x 0 y 3 y 2 y 1 y 0 data pointer (dp) register x ( ) register y (4) specifying ram digit specifying ram file 0 1 01 d 5 d 7 d 0 1 specifying bit position set register y (4) port d output latch mitsubishi electric 9 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 10 rom map of m34282m2/e2 program memory (rom) the program memory is a mask rom. 1 word of rom is composed of 9 bits. rom is separated every 128 words by the unit of page (addresses 0 to 127). table 1 rom size and pages fig. 11 ram map page 2 (addresses 0100 16 to 017f 16 ) is the special page for subroutine calls. subroutines written in this page can be called from any page with the 1-word instruction (bm). subroutines extending from page 2 to another page can also be called with the bm instruction when it starts on page 2. rom pattern of all addresses can be used as data areas with the tabp p instruction. data memory (ram) 1 word of ram is composed of 4 bits, but 1-bit manipulation (with the sb j, rb j, and szb j instructions) is enabled for the entire memory area. a ram address is specified by a data pointer. the data pointer consists of registers x and y. set a value to the data pointer certainly when executing an instruction to access ram. table 2 shows the ram size. figure 11 shows the ram map. product m34282m2/e2 m34282m1 rom size ( ? 9 bits) 2048 words 1024 words pages 16 (0 to 15) 8 (0 to 7) product m34282m2/e2 m34282m1 ram size 64 words ? 4 bits (256 bits) 48 words ? 4 bits (128 bits) table 2 ram size register y register x 0 1 2 3 4 5 6 7 0 1 ram 64 words ? 4 bits (256 bits) 23 64 words 8 9 10 11 12 13 14 15 m34282m2/e2 48 words m34282m1 0 87654321 0000 16 0080 16 017 f 16 subroutine special page 007 f 16 00 ff 16 0100 16 07 ff 16 0180 16 page 1 page 2 page 0 page 3 page 15 mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 10 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer fig. 12 auto-reload function timers the 4282 group has the programmable timer. programmable timer the programmable timer has a reload register and enables the frequency dividing ratio to be set. it is decremented from a setting value n. when it underflows (count to n + 1), a timer 1 underflow flag is set to ?,?new data is loaded from the reload register, and count continues (auto-reload function). ff 16 n 00 16 n: counter initial value count starts reload reload 1st underflow 2nd underflow n+1 count n+1 count time a skip instruction is executed timer 1 underflow flag the contents of counter 1 0 the 4282 group timer consists of the following circuit. timer 1 : 8-bit programmable timer timer 2 : 8-bit programmable timer these timers can be controlled with the timer control registers v1 and v2. each timer function is described below. table 3 function related timer circuit timer 1 timer 2 14-bit timer structure 8-bit programmable binary down counter 8-bit programmable binary down counter 14-bit fixed frequency count source carrier wave output (carry) bit 5 of watchdog timer f(x in ) f(x in )/2 instruction clock frequency dividing ratio 1 to 256 1 to 256 16384 use of output signal carrier wave output control carrier wave output watchdog timer timer 1 count source control register v1 v2 mitsubishi electric preliminar y notice: this is not a final specification. som e parametric limits are subject to change. 11 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer fig. 13 timers structure x in frequency divider (divided by 4) instck (instruction clock) frequency divider (divided by 8) stck (system clock) initializing signal wrst instruction system reset instck q s r cck instruction initializing signal (note 4) (note 3) synchronous circuit 14-bit timer (wdt) 13 0 5 initializing signal (note 4) wdf1 wdf2 (note 1) 0 1 v1 0 carry 1 0 v1 1 reload register r1 (8) timer 1 (8) register b register a (t1ab) (tab1) (note 2) t1f snzt1 instruction timer 1 underflow signal (to port carr) register a register a reload control circuit (tab2) v2 2 q r t t2f register b (t2ab) reload register r2l (8) timer 2(8) register b (t2hab) reload register r2h (8) 0 1 v2 0 (note 1) v2 1 0 1 (tab2) (t2ab) carryd (to port carr) t2f v2 3 snzt2 instruction x in d t q r v1 0 carrier wave output control signal v1 2 port carr scar instruction sq r rcar instruction car flag carry (to timer 1) timer 1 underflow signal (t2r2l) (tab1) (note 3) 1/2 notes 1: counting is stopped by clearing to 0. 2: when the t1ab instruction is executed after v1 0 is set to 1, writing is performed only to reload register r1. 3: the data of reload register r2l set with the t2ab instruction can be also written to timer 2 with the t2r2l instruction. 4: the initializing signal is output at reset or ram back-up mode. mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 12 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer table 4 control registers related to timer v1 2 v1 1 v1 0 timer control register v1 auto-control output by timer 1 is invalid auto-control output by timer 1 is valid carrier wave output (carry) bit 5 of watchdog timer (wdt) stop (timer 1 state retained) operating 0 1 0 1 0 1 carrier wave output auto-control bit timer 1 count source selection bit timer 1 control bit at reset : 000 2 w at ram back-up : 000 2 v1 3 v1 2 v1 1 v1 0 timer control register v1 to expand h interval is invalid to expand h interval is valid (when v2 2 =1 selected) carrier wave generation function invalid carrier wave generation function valid f(x in ) f(x in )/2 stop (timer 2 state retained) operating 0 1 0 1 0 1 0 1 carrier wave h interval expansion bit carrier wave generation function control bit timer 2 count source selection bit timer 2 control bit at reset : 0000 2 w at ram back-up : 0000 2 note: w represents write enabled. (1) control registers related to timer timer control register v1 register v1 controls the timer 1 count source and auto- control function of carrier wave output from port carr by timer 1. set the contents of this register through register a with the tv1a instruction. timer control register v2 register v2 controls the timer 2 count source and the carrier wave generation function by timer. set the contents of this register through register a with the tv2a instruction. (2) precautions note the following for the use of timers. count source stop timer 1 counting to change its count source. watchdog timer be sure that the timing to execute the wrst instruction in order to operate wdt efficiently. writing to reload register r1 when writing data to reload register r1 while timer 1 is operating, avoid a timing when timer 1 underflows. stop of timer 2 avoid a timing when timer 2 underflows to stop timer 2. writing to reload register r2h when writing data to reload register r2h while timer 2 is operating, avoid a timing when timer underflows. timer 2 carrier wave output function when to expand h interval of carrier wave is valid, set 1 or more to reload register r2h. mitsubishi electric preliminar y notice: this is not a final specification. som e parametric limits are subject to change. 13 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer (3) timer 1 timer 1 is an 8-bit binary down counter with the timer 1 reload register (r1). when timer is stopped, data can be set simultaneously in timer 1 and the reload register (r1) with the t1ab instruction. when timer is operating, data can be set to only reload register r1 with the t1ab instruction. when setting the next count data to reload register r1 at operating, set data before timer 1 underflows. timer 1 starts counting after the following process; ? set data in timer 1, ? select the count source with the bit 1 of register v1, and ? set the bit 0 of register v1 to ?. once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes ??, the timer 1 underflow flag (t1f) is set to ?,?new data is loaded from reload register r1, and count continues (auto-reload function). when a value set in reload register r1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). data can be read from timer 1 to registers a and b. when reading the data, stop the counter and then execute the tab1 instruction. (4) timer 2 timer 2 is an 8-bit binary down counter with the timer 2 reload registers (r2h and r2l). data can be set simultaneously in timer 2 and the reload register (r2l) with the t2ab instruction. the contents of reload register (r2l) set with the t2ab instruction can be set again to timer 2 with the t2r2l instruction. data can be set to reload register (r2h) with the t2hab instruction. timer 2 starts counting after the following process; ? set data in timer 2, ? select the count source with the bit 1 of register v2, and ? select the valid/invalid of the carrier wave generation function by bit 2 of register v1 (when this function is valid, select the valid/invalid of the carrier wave ??interval expansion by bit 3), and ? set the bit 0 of register v1 to ?. when the carrier wave generation function is invalid (v2 2 =??, the following operation is performed; once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes ??, the timer 2 underflow flag (t2f) is set to ?,?new data is loaded from reload register r2l, and count continues (auto-reload function). when a value set in reload register r2l is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). when the carrier wave generation function is valid (v2 2 =??, the carrier wave which has the ??interval set to the reload register r2l and ??interval set to the reload register r2h can be output. after the count of the ??interval of carrier wave is started, timer 2 underflows and the timer 2 underflow flag (t2f) is set to ?? then, the ??interval data of carrier wave is reloaded from the reload register r2h, and count continues. when timer underflows again after auto-reload, the t2f flag is set to ?? and then, the ??interval data of carrier wave is reloaded from the reload register r2l, and count continues. after that, each timer underflows, data is reloaded from reload register r2h and r2l alternately. when a value set in reload register r2h is n, ??interval of carrier wave is as follows; ? when to expand ??interval is invalid (v2 3 = ??, count source ? (n+1), n = 0 to 255 ? when to expand ??interval is valid (v2 3 = ??, count source ? (n+1.5), n = 1 to 255 when a value set in reload register r2l is m, ??interval of carrier wave is as follows; count source ? (m+1), m = 0 to 255 data can be read from timer 2 to registers a and b. when reading the data, stop the counter and then execute the tab2 instruction. (5) timer underflow flags (t1f, t2f) timer 1 underflow flag or timer 2 underflow flag is set to ? when the timer 1 or timer 2 underflows. the state of flags t1f and t2f can be examined with the skip instruction (snzt1, snzt2). flags t1f and t2f are cleared to ??when the next instruction is skipped with a skip instruction. mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 14 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer fig. 15 carrier wave generation example by timer 2 fig. 14 port carr output control by timer 1 port carr output r e g i s t e r v 1 2 a b c ? s e t t h e i n t e r v a l a t o t i m e r 1 . ? s e t t h e i n t e r v a l b t o r e l o a d r e g i s t e r r 1 . ? set the interval c to reload register r1. ? set the interval d to reload register r1. d t i m e r 1 u n d e r f l o w port carr output carrier wave output start t i m e r 1 s t a r t s c a r r i e r w a v e o u t p u t s t a r t c o u n t s o u r c e c a r r y s e l e c t e d a u t o - c o n t r o l v a l i d a u t o - c o n t r o l i n v a l i d auto-control invalid t i m e r 1 s t o p carrier wave output stop ( n o t e ) 7 7 7 7 c a r r y t i m e r 1 u n d e r f l o w h l 1 0 h l 1 0 h l 1 0 n o t e : w h e n t i m e r 1 i s s t o p p e d , t h e p o r t c a r r o u t p u t a u t o - c o n t r o l i s t e r m i n a t e d r e g a r d l e s s o f b i t 2 ( v 1 2 ) o f r e g i s t e r v 1 . ( r 2 l ) ( r 2 h ) ( r 2 l ) ( r 2 h ) ( r 2 l ) ( r 2 h ) c a r r y d ( r 2 l ) ( r 2 h ) (r2l) ( r 2 h )(r2l) ( r 2 h ) t i m e r 2 c o u n t s o u r c e t i m e r 2 c o u n t v a l u e ( r e l o a d r e g i s t e r ) t i m e r 2 u n d e r f l o w s i g n a l c a r r y d t i m e r 2 s t a r t s c a r r i e r w a v e p e r i o d : 7 c l o c k s t o e x p a n d h i n t e r v a l o f c a r r i e r w a v e i s i n v a l i d ( v 2 3 = 0 ) y [ c o u n t s o u r c e : 4 . 0 m h z , r e s o l u t i o n : 2 5 0 n s ] t o e x p a n d h i n t e r v a l o f c a r r i e r w a v e i s v a l i d ( v 2 3 = 1 ) y [ w h e n c o u n t s o u r c e i s 4 . 0 m h z , c a r r i e r w a v e i s e x p a n d e d f o r 1 2 5 n s ] 02 16 0 1 1 6 0 0 1 6 03 16 0 2 1 6 01 16 0 2 1 6 0 1 1 6 00 16 0 2 1 6 0 1 1 6 00 16 02 16 01 16 00 16 0 3 1 6 0 2 1 6 0 1 1 6 0 0 1 6 0 3 1 6 0 2 1 6 01 16 0 0 1 6 03 16 0 2 1 6 02 16 0 1 1 6 0 0 1 6 0 2 1 6 0 1 1 6 00 16 02 16 0 1 1 6 00 16 0 3 1 6 0 2 1 6 0 1 1 6 0 0 1 6 0 3 1 6 3 c l o c k s i n t e r v a l t i m e r 2 c o u n t s o u r c e t i m e r 2 c o u n t v a l u e ( r e l o a d r e g i s t e r ) t i m e r 2 u n d e r f l o w s i g n a l timer 2 starts 3 clocks interval c a r r i e r w a v e p e r i o d : 7 c l o c k s c a r r i e r w a v e p e r i o d : 7 . 5 c l o c k s 3 . 5 c l o c k s i n t e r v a l 3 . 5 c l o c k s i n t e r v a l c a r r i e r w a v e p e r i o d : 7 . 5 c l o c k s n o t e : w h e n t o e x p a n d h i n t e r v a l o f t h e c a r r i e r w a v e i s v a l i d , s e t 0 1 1 6 o r m o r e t o r e l o a d r e g i s t e r r 2 h . i n t h i s c a s e , t h e f o l l o w i n g i s s e t ; t i m e r 2 c a r r i e r w a v e g e n e r a t i o n f u n c t i o n i s v a l i d ( v 2 2 = 1 ) , l i n t e r v a l ( 0 3 1 6 ) o f c a r r i e r w a v e i s s e t t o r e l o a d r e g i s t e r r 2 l h i n t e r v a l ( 0 2 1 6 ) o f c a r r i e r w a v e i s s e t t o r e l o a d r e g i s t e r r 2 h mitsubishi electric preliminar y notice: this is not a final specification. som e parametric limits are subject to change. 15 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer fig. 16 timer 2 count start/stop timing (r2l) (r2h) (r2l) timer 2 count value (reload register) timer 2 underflow signal carryd timer 2 count start timing timer 2 count start timing instruction clock =f(x in )/8 machine cycle tv2a instruction execution cycle (v2 0 ) to expand h interval of carrier wave is invalid (v2 3 = 0 ), timer 2 carrier wave generation function is valid (v2 2 = 1 ), count source x in /2 selected (v2 1 = 1 ), l interval (03 16 ) of carrier wave is set to reload register r2l h interval (02 16 ) of carrier wave is set to reload register r2h notes 1: when the carrier wave generation function is vaild (v2 2 = 1 ), avoid a timing when timer 2 underflows to stop timer 2. when the timer 2 count stop occurs at the same timing with the timer 2 underflows, hazard may occur in the carrier wave output waveform. 2: when the timer 2 is stopped during h output of carrier wave while the carrier wave generation function is valid, it is stopped after the h interval set by reload register r2h is output. mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer logic operation function the 4282 group has the 4-bit logic operation function. the logic operation between the contents of register a and the low-order 4 bits of register e is performed and its result is stored in register a. each logic operation can be selected by setting logic operation selection register lo. set the contents of this register through register a with the tloa instruction. the logic operation selected by register lo is executed with the lgop instruction. table 5 shows the logic operation selection register lo. table 5 logic operation selection register lo at reset : 00 2 at ram back-up : 00 2 w l o 1 0 0 1 1 l o 0 0 1 0 1 lo 1 lo 0 logic operation selection bits logic operation selection register lo logic operation function exclusive logic or operation (xor) or operation (or) and operation (and) not available note: ??represents write enabled. watchdog timer watchdog timer provides a method to reset and restart the system when a program runs wild. watchdog timer consists of 14-bit timer (wdt) and watchdog timer flags (wdf1, wdf2). watchdog timer downcounts the instruction clock (instck) as the count source immediately after system is released from reset. when the timer wdt count value becomes 0000 16 and underflow occurs, the wdf1 flag is set to ?.?then, when the wrst instruction is not executed before the timer wdt counts 16383, wdf2 flag is set to ??and internal reset signal is generated and system reset is performed. execute the wrst instruction at period of 16383 machine cycle or less to keep the microcomputer operation normal. timer wdt is also used for generation of oscillation stabilization time. when system is returned from reset and from ram back- up mode by key-input, software starts after the stabilization oscillation time until timer wdt downcounts to 3e00 16 elapses. fig. 17 watchdog timer function value of timer wdt wdf2 flag wrst instruction execution s y s t e m r e s e t return 3 e 0 0 1 6 0 0 0 0 1 6 w d f 1 f l a g 3 f f f 1 6 s y s t e m r e s e t s o f t w a r e s t a r t s o f tware start s o f t w a r e s t a r t pof instruction execution i n t e r n a l r e s e t s i g n a l 1 0 1 0 h l mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 17 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer fig. 18 reset release timing reset function the 4282 group has the power-on reset circuit, though it does not have reset pin. system reset is performed automatically at power-on, and software starts program from address 0 in page 0. in order to make the built-in power-on reset circuit operate efficiently, set the voltage rising time until v dd = 0 to 2.2 v is obtained at power-on 1ms or less. fig. 19 power-on reset circuit example f(x in ) internal reset signal f(x in ) 16384 pulses software operation starts (address 0 in page 0) h l v dd internal reset signal power-on reset circuit voltage drop detection circuit watchdog timer output power-on reset circuit output voltage reset state internal reset signal reset released power-on mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 18 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer (1) internal state at reset table 6 shows port state at reset, and figure 20 shows internal state at reset (they are retained after system is released from reset). the contents of timers, registers, flags and ram except shown in figure 20 are undefined, so set the initial value to them. 00000000000 0 0 0 000 0000 0 0000 0000 00 0 0 1111 1111 00 0000 11 fig. 20 internal state at reset table 6 port state at reset name d 0 ? 3 d 4 ? 7 g 0 ? 3 e 0 , e 1 carr state at reset high impedance state high impedance state (pull-down transistor off) high impedance state (pull-down transistor off) high impedance state (pull-down transistor off) ??output note: the contents of all output latch is initialized to ?. voltage drop detection circuit the built-in voltage drop detection circuit is designed to detect a drop in voltage at operating and to reset the microcomputer if the supply voltage drops below the specified value (typ. 1.50 v) or less. fig. 21 voltage drop detection circuit operation waveform the voltage drop detection circuit is stopped and power dissipation is reduced in the ram back-up mode with the initialized cpu stopped. ?program counter (pc) .............................................................. address 0 in page 0 is set to program counter. ?power down flag (p) ................................................................. ?timer 1 underflow flag (t1f) ................................................... ?timer 2 underflow flag (t2f) ................................................... ?timer control register v1 .......................................................... ?timer control register v2 .......................................................... ?port carr output flag (car) .................................................. ?pull-down control register pu0 ................................................ ?pull-down control register pu1 ................................................ ?logic operation selection register lo ...................................... ?most significant rom code reference enable flag (urs) ?carry flag (cy) ......................................................................... ?register a ................................................................................. ?register b ................................................................................. ?register x ................................................................................. ?register y ................................................................................. ?stack pointer (sp) .................................................................... 7 % % * o u f s o b m s f t f u t j h o b m 3 f t f u w p m u b h f 5 : 1 7 / p u f / p u f 5 i f w p m u b h f e s p q e f u f d u j p o d j s d v j u e p f t o p u i b w f u i f i z t u f s f t j t d i b s b d u f s j t u j d t j o u i f e f u f d u f e w p m u b h f microcomputer starts operation after f(x in ) is counted to 16384 times. mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 19 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer ram back-up mode the 4282 group has the ram back-up mode. when the pof instruction is executed, system enters the ram back-up state. as oscillation stops retaining ram, the functions and states of reset circuit at ram back-up mode, power dissipation can be reduced without losing the contents of ram. table 7 shows the function and states retained at ram back-up. figure 22 shows the state transition. (1) warm start condition when the external wakeup signal is input after the system enters the ram back-up state by executing the pof instruction, the cpu starts executing the software from address 0 in page 0. in this case, the p flag is 1. (2) cold start condition the cpu starts executing the software from address 0 in page 0 when any of the following conditions is satisfied . reset by power-on reset circuit is performed reset by watchdog timer is performed reset by voltage drop detection circuit is performed in this case, the p flag is 0. (3) identification of the start condition warm start (return from the ram back-up state) or cold start (return from the normal reset state) can be identified by examining the state of the power down flag (p) with the snzp instruction. table 7 functions and states retained at ram back-up ram back-up ? o ? o o o ? o ? ? ? ? ? ? function program counter (pc), registers a, b, carry flag (cy), stack pointer (sp) (note 2) contents of ram port carr ports d 0 d 7 ports e 0 , e 1 port g timer control registers v1, v2 pull-down control registers pu0, pu1 logic operation selection register lo timer 1 function, timer 2 function timer underflow flags (t1f, t2f) watchdog timer (wdt) watchdog timer flags (wdf1, wdf2) most significant rom code reference enable flag (urs) notes 1: o represents that the function can be retained, and ? represents that the function is initialized. registers and flags other than the above are undefined at ram back-up, and set an initial value after returning. 2:the stack pointer (sp) points the level of the stack register and is initialized to 11 2 at ram back-up. fig. 22 state transition fig. 23 set source and clear source of the p flag fig. 24 start condition identified example using the snzp instruction : microcomputer starts its operation after f(x in ) is counted to16384 times. stabilizing time a pof instruction is executed a f(x in ) oscillation return input b (ram back-up mode) f(x in ) stop reset (stabilizing time a ) (stabilizing time a ) s r q power down flag p pof instruction reset input set source pof instruction is executed clear source reset input software start p = 1 ? yes warm start cold start no mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 20 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer remarks only key-on wakeup function of the port whose pull-down transistor is turned on by register pu1 is valid. only key-on wakeup function of the port whose pull-down transistor is turned on by register pu0 is valid. key-on wakeup function is always valid. return source ports d 4 d 7 ports e 0 , e 1 , g ports e 2 return condition return by an external h level input. return by an external h level input. return by an external h level input. table 8 return source and return condition (5) pull-down control register registers pu0 and pu1 are 4-bit registers and control the on/off of pull-down transistor and key-on wakeup function for ports e 0 , e 1 , g and ports d 4 d 7 . table 9 pull-down control registers pu0 3 pu0 2 pu0 1 pu0 0 pull-down transistor off, key-on wakeup invalid pull-down transistor on, key-on wakeup valid pull-down transistor off, key-on wakeup invalid pull-down transistor on, key-on wakeup valid pull-down transistor off, key-on wakeup invalid pull-down transistor on, key-on wakeup valid pull-down transistor off, key-on wakeup invalid pull-down transistor on, key-on wakeup valid ports g 2 , g 3 pull-down transistor control bit ports g 0 , g 1 pull-down transistor control bit port e 1 pull-down transistor control bit port e 0 pull-down transistor control bit pull-down control register pu0 at reset : 0000 2 at ram back-up : state retained w 0 1 0 1 0 1 0 1 note: w represents write enabled. set the contents of register pu0 or pu1 through register a with the tpu0a or tpu1a instruction, respectively. (4) return signal an external wakeup signal is used to return from the ram back-up mode. table 8 shows the return condition for each return source. pu1 3 pu1 2 pu1 1 pu1 0 pull-down transistor off, key-on wakeup invalid pull-down transistor on, key-on wakeup valid pull-down transistor off, key-on wakeup invalid pull-down transistor on, key-on wakeup valid pull-down transistor off, key-on wakeup invalid pull-down transistor on, key-on wakeup valid pull-down transistor off, key-on wakeup invalid pull-down transistor on, key-on wakeup valid port d 7 pull-down transistor control bit port d 6 pull-down transistor control bit port d 5 pull-down transistor control bit port d 4 pull-down transistor control bit pull-down control register pu1 at reset : 0000 2 at ram back-up : state retained w 0 1 0 1 0 1 0 1 mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 21 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer fig. 25 clock control circuit structure system clock signal f(x in ) is obtained by externally connecting a ceramic resonator. connect this external circuit to pins x in and x out at the shortest distance as shown figure 26. a feedback resistor is built-in between x in pin and x out pin. rom ordering method please submit the information described below when ordering mask rom. (1) mask rom order confirmation form ................................. 1 (2) data to be written into mask rom .......................... eprom (three sets containing the identical data) (3) mark specification form .................................................... 1 fig. 26 ceramic resonator external circuit clock control the clock control circuit consists of the following circuits. system clock generating circuit control circuit to stop the clock oscillation control circuit to return from the ram back-up state o s c r s q p o f i n s t r u c t i o n x i n x o u t ports e 0 ,e 1 ,g 0 g 3 pull-down control register pu0 p o r t e 2 internal clock generation circuit (divided by 4) f r e q u e n c y d i v i d e r ( d i v i d e d b y 8 ) cck instruction s t c k i n s t c k i n t e r n a l p o w e r - o n r e s e t c i r c u i t ports d 4 7 pull-down control register 1 multi- plexer 4282 x in x out c in c out 45 use the resonator manufacturer s recommended value because constants such as capacitance depend on the resonator. mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 22 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer list of precautions ? noise and latch-up prevention connect a capacitor on the following condition to prevent noise and latch-up; connect a bypass capacitor (approx. 0.01 f) between pins v dd and v ss at the shortest distance, equalize its wiring in width and length, and use the thickest wire. in the one time prom version, port e 2 is also used as v pp pin. connect this pin to v ss through the resistor about 5 k ? which is assigned to e 2 /v pp pin as close as possible at the shortest distance. ? notes on unused pins (note in order to set the output latch to 0 to make pins open) after system is released from reset, a port is in a high- impedance state until the output latch of the port is set to 0 by software. accordingly, the voltage level of pins is undefined and the excess of the supply current may occur. to set the output latch periodically is recommended because the value of output latch may change by noise or a program run away (caused by noise). (note when connecting to v ss and v dd ) connect the unused pins to v ss and v dd at the shortest distance and use the thick wire against noise. ? timer count source stop timer 1 counting to change its count source. watchdog timer be sure that the timing to execute the wrst instruction in order to operate wdt efficiently. writing to reload register r1 when writing data to reload register r1 while timer 1 is operating, avoid a timing when timer 1 underflows. stop of timer 2 avoid a timing when timer 2 underflows to stop timer 2. writing to reload register r2h when writing data to reload register r2h while timer 2 is operating, avoid a timing when timer underflows. timer 2 carrier wave output function when to expand h interval of carrier wave is valid, set 1 or more to reload register r2h. ? program counter make sure that the program counter does not specify after the last page of the built-in rom. mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 23 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer instructions the 4282 group has the 68 instructions. each instruction is described as follows; (1) list of instruction function (2) machine instructions (index by alphabet) (3) machine instructions (index by function) (4) instruction code table symbol the symbols shown below are used in the following list of instruction function and the machine instructions. symbol a b dr er v1 v2 pu0 pu1 lo x y dp pc pc h pc l sk sp cy r1 t1 t1f r2h r2l t2 t2f wdt wdf1 wdf2 urs p stck instck contents register a (4 bits) register b (4 bits) register d (3 bits) register e (8 bits) timer control register v1 (3 bits) timer control register v2 (4 bits) pull-down control register pu0 (4 bits) pull-down control register pu1 (4 bits) logic operation selection register lo (2 bits) register x (2 bits) register y (4 bits) data pointer (6 bits) (it consists of registers x and y) program counter (11 bits) high-order 4 bits of program counter low-order 7 bits of program counter stack register (11 bits ? 4) stack pointer (2 bits) carry flag timer 1 reload register timer 1 timer 1 underflow flag timer 2 reload register timer 2 reload register timer 2 timer 2 underflow flag watchdog timer watchdog timer flag 1 watchdog timer flag 2 most significant rom code reference enable flag power down flag system clock instruction clock contents port d (8 bits) port e (3 bits) port g (4 bits) port carr (1 bit) car flag (1 bit) hexadecimal variable hexadecimal variable hexadecimal variable hexadecimal constant which represents the immediate value hexadecimal constant which represents the immediate value binary notation of hexadecimal variable a (same for others) direction of data movement data exchange between a register and memory decision of state shown before ? contents of registers and memories negate, flag unchanged after executing instruction ram address pointed by the data pointer label indicating address a 6 a 5 a 4 a 3 a 2 a 1 a 0 label indicating address a 6 a 5 a 4 a 3 a 2 a 1 a 0 in page p 3 p 2 p 1 p 0 hex. number c + hex. number x (also same for others) symbol d e g carr car x y p n j a 3 a 2 a 1 a 0 ? ? ( ) m(dp) a p, a c + x note : the 4282 group just invalidates the next instruction when a skip is performed. the contents of program counter is not increased by 2. accordingly, the number of cycles does not change even if skip is not performed. however, the cycle count becomes ??if the tabp p, rt, or rts instruction is skipped. mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 24 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer function (a) n n = 0 to 15 (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p p=0 to 15 (pc l ) (dr 2 dr 0 , a 3 a 0 ) when urs=0 (b) (rom(pc)) 7 to 4 (a) (rom(pc)) 3 to 0 when urs=1 (cy) (rom(pc)) 8 (b) (rom(pc)) 7 to 4 (a) (rom(pc)) 3 to 0 (pc) (sk(sp)) (sp) (sp) 1 (a) (a) + (m(dp)) (a) (a) + (m(dp)) + (cy) (cy) carry (a) (a) + n n = 0 to 15 (cy) 1 (cy) 0 (cy) = 0 ? (a) (a) cy a 3 a 2 a 1 a 0 logic operation instruction xor, or, and (mj(dp)) 1 j = 0 to 3 (mj(dp)) 0 j = 0 to 3 (mj(dp)) = 0 ? j = 0 to 3 list of instruction function arithmetic operation register to register transfer grouping mnemonic tab tba tay tya teab tabe tda lxy x, y iny dey tam j xam j xamd j xami j function (a) (b) (b) (a) (a) (y) (y) (a) (er 7 er 4 ) (b) (er 3 er 0 ) (a) (b) (er 7 er 4 ) (a) (er 3 er 0 ) (dr 2 dr 0 ) (a 2 a 0 ) (x) x, x = 0 to 3 (y) y, y = 0 to 15 (y) (y) + 1 (y) (y) 1 (a) (m(dp)) (x) (x) exor(j) j = 0 to 3 (a) (m(dp)) (x) (x) exor(j) j = 0 to 3 (a) (m(dp)) (x) (x) exor(j) j = 0 to 3 (y) (y) 1 (a) (m(dp)) (x) (x) exor(j) j = 0 to 3 (y) (y) + 1 grouping mnemonic la n tabp p am amc a n sc rc szc cma rar lgop sb j rb j szb j ram to register transfer ram addresses bit operation page 38 40 40 42 41 39 40 31 31 30 40 43 43 43 page 31 39 27 27 27 35 33 37 30 33 31 34 33 37 mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 25 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer comparison operation grouping mnemonic seam sea n b a bl p, a ba a bla p, a bm a bml p, a bmla p, a rt rts function (a) = (m(dp)) ? (a) = n ? n = 0 to 15 (pc l ) a 6 ? 0 (pc h ) p (pc l ) a 6 ? 0 (pc l ) (a 6 ? 4 , a 3 ? 0 ) (pc h ) p (pc l ) (a 6 ? 4 , a 3 ? 0 ) (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) 2 (pc l ) a 6 ? 0 (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p p= 0 to 15 (pc l ) a 6 ? 0 (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p p= 0 to 15 (pc l ) (a 6 ? 4 , a 3 ? 0 ) (pc) (sk(sp)) (sp) (sp) ?1 (pc) (sk(sp)) (sp) (sp) ?1 subroutine operation return operation branch operation grouping mnemonic tv1a tab1 t1ab snzt1 tv2a tab2 t2ab t2hab t2r2l snzt2 function (v1 2 ?1 0 ) (a 2 ? 0 ) (b) (t1 7 ?1 4 ) (a) (t1 3 ?1 0 ) at timer 1 stop (v1 0 =0): (r1 7 ?1 4 ) (b) (t1 7 ?1 4 ) (b) (r1 3 ?1 0 ) (a) (t1 3 ?1 0 ) (a) at timer 1 operating (v1 0 =1): (r1 7 ?1 4 ) (b) (r1 3 ?1 0 ) (a) (t1f) = 1 ? after skipping the next instruction (t1f) 0 (v2 3 ?2 0 ) (a 3 ? 0 ) (b) (t2 7 ?2 4 ) (a) (t2 3 ?2 0 ) (r2l 7 ?2l 4 ) (b) (t2 7 ?2 4 ) (b) (r2l 3 ?2l 0 ) (a) (t2 3 ?2 0 ) (a) (r2h 7 ?2h 4 ) (b) (r2h 3 ?2h 0 ) (a) (t2 7 ?2 4 ) (r2l 7 ?2l 4 ) (t2 7 ?2 4 ) (r2l 3 ?2l 0 ) (t2f) = 1 ? after skipping the next instruction (t2f) 0 timer operation page 36 35 27 28 28 28 28 29 29 34 34 page 42 39 37 36 42 39 38 38 38 36 mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 26 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer list of instruction function (continued) input/output operation grouping mnemonic cld rd sd szd oea iae oga iag scar rcar nop pof snzp cck tloa ursc tpu0a tpu1a wrst function (d) 0 (d(y)) 0 (y) = 0 to 7 (d(y)) 1 (y) = 0 to 7 (d(y)) = 0 ? (y) = 4 to 7 (e 1 , e 0 ) (a 1 , a 0 ) (a 2 a 0 ) (e 2 e 0 ) (g) (a) (a) (g) (car) 1 (car) 0 (pc) (pc) + 1 ram back-up (p) = 1 ? stck changes to f(x in ) (lo 1 , lo 0 ) (a 1 , a 0 ) (urs) 1 (pu0 3 pu0 0 ) (a 3 a 0 ) (pu1 3 pu1 0 ) (a 3 a 0 ) (wdf1) 0 other operation carrier wave control operation page 29 34 35 37 32 30 32 30 35 33 32 32 36 29 41 42 41 41 43 4282 group mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. 27 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 machine instructions (index by alphabet) a n (add n and accumulator) 01010n 3 n 2 n 1 n 0 0an 11 overflow = 0 grouping: arithmetic operation description: adds the value n in the immediate field to register a. the contents of carry flag cy remains un- changed. skips the next instruction when there is no overflow as the result of operation. operation: (a) (a) + n n = 0 to 15 am (add accumulator and memory) 000001010 00a 11 grouping: arithmetic operation description: adds the contents of m(dp) to register a. stores the result in register a. the contents of carry flag cy remains unchanged. operation: (a) (a) + (m(dp)) amc (add accumulator, memory and carry) 000001011 00b 11 0/1 grouping: arithmetic operation description: adds the contents of m(dp) and carry flag cy to register a. stores the result in regis- ter a and carry flag cy. operation: (a) (a) + (m(dp)) + (cy) (cy) carry b a (branch to address a) 11a 6 a 5 a 4 a 3 a 2 a 1 a 0 1a 11 grouping: branch operation description: branch within a page : branches to address a in the identical page. operation: (pc l ) a 6 ? 0 8 +a skip condition number of cycles number of words instrunction code d 8 d 0 28 4282 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 bm a (branch and mark to address a in page 2) 10a 6 a 5 a 4 a 3 a 2 a 1 a 0 1aa 11 grouping: subroutine call operation description: call the subroutine in page 2 : calls the subroutine at address a in page 2. operation: (sk(sp)) (pc) (sp) (sp) + 1 (pc h ) 2 (pc l ) a 6 ? 0 bl p, a (branch long to address a in page p) 00011p 3 p 2 p 1 p 0 03p 22 grouping: branch operation description: branch out of a page : branches to address a in page p. note: p is 0 to 7 for m34282m1, p is 0 to 15 for m34282m2/e2. operation: (pc h ) (p) (pc l ) a 6 ? 0 bla p, a (branch long to address a in page p) 000010000 010 22 grouping: branch operation description: branch within a page : branches to address (a 6 a 5 a 4 a 3 a 2 a 1 a 0 ) determined by replac- ing the low-order 4 bits of the address a in page p with register a. note: p is 0 to 7 for m34282m1, p is 0 to 15 for m34282m2/e2. 2 16 11a 6 a 5 a 4 a 3 a 2 a 1 a 0 1a 8 +a operation: (pc h ) (p) (pc l ) (a 6 ? 4 , a 3 ? 0 ) 2 16 11a 6 a 5 a 4 p 3 p 2 p 1 p 0 1p ba a (branch to address a + accumulator) 000000001 001 22 grouping: branch operation description: branch within a page : branches to address (a 6 a 5 a 4 a 3 a 2 a 1 a 0 ) determined by replac- ing the low-order 4 bits of the address a in the identical page with register a. operation: (pc l ) a 6 ? 4 , a 3 ? 0 2 16 11a 6 a 5 a 4 a 3 a 2 a 1 a 0 1a 8 +a 8 +a 4282 group mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. 29 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 bml p, a (branch and mark long to address a in page p) 00111p 3 p 2 p 1 p 0 07p 22 grouping: subroutine call operation description: call the subroutine : calls the subroutine at address a in page p. note: p is 0 to 7 for m34282m1, p is 0 to 15 for m34282m2/e2. operation: (sk(sp)) (pc) (sp) (sp) + 1 (pc h ) p (pc l ) a 6 ? 0 bmla p, a (branch and mark long to address a in page p) 001010000 050 22 grouping: subroutine call operation description: call the subroutine : calls the subroutine at address (a 6 a 5 a 4 a 3 a 2 a 1 a 0 ) determined by replacing the low-order 4 bits of address a in page p with register a. note: p is 0 to 7 for m34282m1, p is 0 to 15 for m34282m2/e2. cck (change system clock to f(x in )) 001011001 059 11 grouping: other operation description: changes system clock (stck) from f(x in )/8 to f(x in ). execute this instruction at address 0 in page 0. operation: change to stck = f(x in ) 2 16 10a 6 a 5 a 4 a 3 a 2 a 1 a 0 1aa operation: (sk(sp)) (pc) (sp) (sp) + 1 (pc h ) p (pc l ) (a 6 ? 4 , a 3 ? 0 ) 2 16 10a 6 a 5 a 4 p 3 p 2 p 1 p 0 1ap cld (clear port d) 000010001 011 11 grouping: input/output operation description: clears (0) to port d (high-impedance state). operation: (d) 1 skip condition number of cycles number of words instrunction code d 8 d 0 30 4282 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 iae (input accumulator from port e) 001010110 056 11 grouping: input/output operation description: transfers the contents of port e to register a. operation: (a 2 ? 0 ) (e 2 ? 0 ) iag (input accumulator from port g) 000101000 028 11 grouping: input/output operation description: transfers the contents of port g to register a. operation: (a) (g) cma (complement of accumulator) 000011100 01c 11 grouping: arithmetic operation description: stores the one s complement for register a s contents in register a. operation: (a) (a) dey (decrement register y) 000010111 017 11 (y) = 15 grouping: ram addresses description: subtracts 1 from the contents of register y. as a result of subtraction, when the con- tents of register y is 15, the next instruction is skipped. operation: (y) (y) ?1 4282 group mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. 31 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 iny (increment register y) 000010011 013 11 (y) = 0 grouping: ram addresses description: adds 1 to the contents of register y. as a re- sult of addition, when the contents of register y is 0, the next instruction is skipped. operation: (y) (y) + 1 lgop (logic operation between accumulator and register e) 001000001 041 11 grouping: arithmetic operation description: executes the logic operation selected by logic operation selection register lo be- tween the contents of register a and register e, and stores the result in register a. operation: logic operation xor, or, and lxy x, y (load register x and y with x and y) 011x 1 x 0 y 3 y 2 y 1 y 0 0y 11 continuous description grouping: ram addresses description: loads the value x in the immediate field to register x, and the value y in the immediate field to register y. when the lxy instruc- tions are continuously coded and executed, only the first lxy instruction is executed and other lxy instructions coded continu- ously are skipped. operation: (x) x, x = 0 to 3 (y) y, y = 0 to 15 c +x la n (load n in accumulator) 01011n 3 n 2 n 1 n 0 0bn 11 continuous description grouping: arithmetic operation description: loads the value n in the immediate field to register a. when the la instructions are continuously coded and executed, only the first la in- struction is executed and other la instructions coded continuously are skipped. operation: (a) n n = 0 to 15 skip condition number of cycles number of words instrunction code d 8 d 0 32 4282 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 pof (power off1) 000001101 00d 11 grouping: other operation description: puts the system in ram back-up state. operation: ram back-up nop (no operation) 000000000 000 11 grouping: other operation description: no operation operation: (pc) (pc) + 1 oea (output port e from accumulator) 010000100 084 11 grouping: input/output operation description: outputs the contents of register a to port e. oga (output port g from accumulator) 010000000 080 11 grouping: input/output operation description: outputs the contents of register a to port g. operation: (g) (a) operation: (e 1 , e 0 ) (a 1 , a 0 ) 4282 group mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. 33 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 rar (rotate accumulator right) 000011101 01d 11 0/1 grouping: arithmetic operation description: rotates 1 bit of the contents of register a in- cluding the contents of carry flag cy to the right. operation: cy a 3 a 2 a 1 a 0 rb j (reset bit) 0010011j 1 j 0 04 11 grouping: bit operation description: clears (0) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). operation: (mj(dp)) 0 j = 0 to 3 c +j rc (reset carry flag) 000000110 006 11 0 grouping: arithmetic operation description: clears (0) to carry flag cy. operation: (cy) 0 rcar (reset car flag) 010000110 086 11 grouping: carrier wave control operation description: clears (0) to port carr output flag. operation: (car) 0 skip condition number of cycles number of words instrunction code d 8 d 0 34 4282 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 rts (return form subroutine and skip) 001000101 045 12 skip at uncondition grouping: return operation description: returns from subroutine to the routine called the subroutine, and skips the next in- struction at uncondition. operation: (sp) (sp) ?1 (pc) (sk(sp)) sb j (set bit) 0010111j 1 j 0 05 11 grouping: bit operation description: sets (1) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). operation: (mj(dp)) 0 j = 0 to 3 c +j rd (reset port d specified by register y) 000010100 014 11 grouping: input/output operation description: clears (0) to a bit of port d specified by reg- ister y (high-impedance state). operation: (d(y)) 0 however, (y) = 0 to 7 rt (return from subroutine) 001000100 044 12 grouping: return operation description: returns from subroutine to the routine called the subroutine. operation: (sp) (sp) ?1 (pc) (sk(sp)) 4282 group mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. 35 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 sc (set carry flag) 000000111 007 11 1 grouping: arithmetic operation description: sets (1) to carry flag cy. operation: (cy) 1 sea n (skip equal, accumulator with immediate data n) 000100101 025 22 (a) = n, n = 0 to 15 grouping: comparison operation description: skips the next instruction when the con- tents of register a is equal to the value n in the immediate field. operation: (a) = n ? n = 0 to 15 scar (set car flag) 010000111 087 11 grouping: carrier wave control operation description: sets (1) to port carr output flag (car). operation: (car) 1 sd (set port d specified by register y) 000010101 015 11 grouping: input/output operation description: sets (1) to a bit of port d specified by regis- ter y. operation: (d(y)) 1 (y) = 0 to 7 2 16 01011n 3 n 2 n 1 n 0 0bn skip condition number of cycles number of words instrunction code d 8 d 0 36 4282 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 snzp (skip if non zero condition of power down flag) 000000011 003 11 (p) = 1 grouping: other operation description: skips the next instruction when p flag is ?? after skipping, p flag remains unchanged. snzt1 (skip if non zero condition of timer 1 underflow flag) 001000010 042 11 (t1f) = 1 grouping: timer operation description: skips the next instruction when the con- tents of t1f flag is ?. after skipping, clears (0) to t1f flag. operation: (t1f) = 1 ? after skipping, (t1f) 0 snzt2 (skip if non zero condition of timer 2 inerrupt request flag) 001010010 052 11 (t2f) = 1 grouping: timer operation description: skips the next instruction when the con- tents of t2f flag is ?. after skipping, clears (0) to t2f flag. operation: (t2f) = 1 ? after skipping, (t2f) 0 operation: (p) = 1 ? seam (skip equal, accumulator with memory) 000100110 026 1 1 (a) = (m(dp)) grouping: comparison operation description: skips the next instruction when the con- tents of register a is equal to the contents of m(dp). operation: (a) = (m(dp)) ? 4282 group mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. 37 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 szb j (skip if zero, bit) 0001000j 1 j 0 02j 11 (mj(dp)) = 0 j = 0 to 3 grouping: bit operation description: skips the next instruction when the con- tents of bit j (bit specified by the value j in the immediate field) of m(dp) is ?. operation: (mj(dp)) = 0 ? j = 0 to 3 szc (skip if zero, carry flag) 000101111 02f 11 (cy) = 0 grouping: arithmetic operation description: skips the next instruction when the con- tents of carry flag cy is ?. operation: (cy) = 0 ? szd (skip if zero, port d specified by register y) 000100100 024 22 (d(y)) = 0 (y) = 4 to 7 grouping: input/output operation description: skips the next instruction when a bit of port d specified by register y is ?. t1ab (transfer data to timer 1 and register r1 from accumulator and register b) 001000111 047 11 grouping: timer operation description: at timer 1 stop (v1 0 = 0 ), transfers the con- tents of register a and register b to timer 1 and reload register r1. at timer 1 operating (v1 0 = 1), transfers the contents of register a and register b to re- load register r1. operation: at timer 1 stop (v1 0 =0) (r1 7 ?1 4 ) (b), (r1 3 ?1 0 ) (a) (t1 7 ?1 4 ) (b), (t1 3 ?1 0 ) (a) at timer 1 operating (v1 0 =1) (r1 7 ?1 4 ) (b), (r1 3 ?1 0 ) (a) operation: (d(y)) = 0 ? (y) = 4 to 7 2 16 000101011 02b skip condition number of cycles number of words instrunction code d 8 d 0 38 4282 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 t2hab (transfer data to register r2h accumulator from register b) 010001001 089 11 grouping: timer operation description: transfers the contents of register a and register b to reload register r2h. t2r2l (transfer data to timer 2 from register r2l) 001010011 053 11 grouping: timer operation description: transfers the contents of reload register r2l to timer 2. operation: (t2 7 ?2 4 ) (r2l 7 ?2l 4 ) (t2 3 ?2 0 ) (r2l 3 ?2l 0 ) operation: (r2h 7 ?2h 4 ) (b) (r2h 3 ?2h 0 ) (a) tab (transfer data to accumulator from register b) 000011110 01e 11 grouping: register to register transfer description: transfers the contents of register b to reg- ister a. operation: (a) (b) t2ab (transfer data to timer 2 and register r2l from accumulator and register b) 010001000 088 11 grouping: timer operation description: transfers the contents of registers a and b to timer 2 and timer 2 reload register r2l. operation: (r2l 7 ?2l 4 ) (b) (r2l 3 ?2l 0 ) (a) (t2 7 ?2 4 ) (b) (t2 3 ?2 0 ) (a) 4282 group mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. 39 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 tab1 (transfer data to accumulator and register b from timer 1) 001010111 057 11 grouping: timer operation description: transfers the contents of timer 1 to regis- ters a and b. operation: (b) (t1 7 ?1 4 ) (a) (t1 3 ?1 0 ) tabe (transfer data to accumulator and register b from register e) 000101010 02a 11 grouping: register to register transfer description: transfers the contents of register e to reg- isters a and b. operation: (b) (er 7 ?r 4 ) (a) (er 3 ?r 0 ) tabp p (transfer data to accumulator and register b from program memory in page p) 01001p 3 p 2 p 1 p 0 09p 13 0/1 grouping: arithmetic operation description: transfers bits 7 to 4 to register b and bits 3 to 0 to register a when urs flag is cleared to ?.?these bits 7 to 0 are the rom pattern in address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) speci- fied by registers a and d in page p. transfers bit 8 of rom pattern is transferred to flag cy when urs flag is set to ??(after the ursc instruction is executed). (one of stack is used when the tabp p instruction is executed.) operation: sk(sp)) (pc) , (sp) (sp) + 1 (pc h ) p, p = 0 to 7, (pc l ) (dr 2 ?r 0 , a 3 ? 0 ) when urs = 0, (b) (rom(pc)) 7 to 4 , (a) (rom(pc)) 3 to 0 when urs = 1, (cy) (rom(pc)) 8 (b) (rom(pc)) 7 to 4 , (a) (rom(pc)) 3 to 0 (sp) (sp) ?1, (pc) (sk(sp)) note: p is 0 to 7 for m34282m1, p is 0 to 15 for m34282m2/e2. tab2 (transfer data to accumulator and register b from timer 2) 001000000 040 11 grouping: timer operation description: transfers the contents of timer 2 to regis- ters a and b. operation: (b) (t2 7 ?2 4 ) (a) (t2 3 ?2 0 ) skip condition number of cycles number of words instrunction code d 8 d 0 40 4282 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 tam j (transfer data to accumulator from memory) 0011001j 1 j 0 06j 11 grouping: ram to register transfer description: after transferring the contents of m(dp) to register a, an exclusive or operation is performed between register x and the value j in the immediate field, and stores the re- sult in register x. operation: (a) (m(dp)) (x) (x)exor(j) j = 0 to 3 4 +j tay (transfer data to accumulator from register y) 000011111 01f 11 grouping: register to register transfer description: transfers the contents of register y to regis- ter a. operation: (a) (y) tba (transfer data to register b from accumulator) 000001110 00e 11 grouping: register to register transfer description: transfers the contents of register a to regis- ter b. tda (transfer data to register d from accumulator) 000101001 029 11 grouping: register to register transfer description: transfers the contents of register a to regis- ter d. operation: (dr 2 ?r 0 ) (a 2 ? 0 ) operation: (b) (a) 4282 group mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. 41 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 teab (transfer data to register e from accumulator and register b) 000011010 01a 11 grouping: register to register transfer description: transfers the contents of register a and register b to register e. operation: (er 7 ?r 4 ) (b) (er 3 ?r 0 ) (a) tloa (transfer data to register lo from accumulator) 001011000 058 11 grouping: other operation description: transfers the contents of register a to logic operation selection register lo. operation: (lo 1 , lo 0 ) (a 1 , a 0 ) tpu0a (transfer data to register pu0 from accumulator) 010001111 08f 11 grouping: other operation description: transfers the contents of register a to pull- up control register pu0. operation: (pu0 3 ?u0 0 ) (a 3 ? 0 ) tpu1a (transfer data to register pu1 from accumulator) 010001110 08e 11 grouping: other operation description: transfers the contents of register a to pull- up control register pu1. operation: (pu1 3 ?u1 0 ) (a 3 ? 0 ) skip condition number of cycles number of words instrunction code d 8 d 0 42 4282 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 tv1a (transfer data to register v1 from accumulator) 001010111 05b 11 grouping: timer operation description: transfers the contents of register a to regis- ter v1. operation: (v1 2 ?1 0 ) (a 2 ? 0 ) tv2a (transfer data to register v2 from accumulator) 001011010 05a 11 grouping: timer operation description: transfers the contents of register a to regis- ter v2. operation: (v2 3 ?2 0 ) (a 3 ? 0 ) ursc (sets upper rom code reference enable flag) 010000010 082 11 grouping: other operation description: sets the most significant rom code refer- ence enable flag (urs) to ?. operation: (urs) 1 tya (transfer data to regiser y from accumulator) 000001100 00c 11 grouping: register to register transfer description: transfers the contents of register a to regis- ter y. operation: (y) (a) 4282 group mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. 43 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 skip condition number of cycles number of words instrunction code d 8 d 0 flag cy 2 16 wrst (watchdog timer reset) 000001111 00f 11 grouping: other operation description: initializes the watchdog timer flag (wdf1). operation: (wdf1) 0 xam j (exchange accumulator and memory data) 0011000j 1 j 0 06j 11 grouping: ram to register transfer description: after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between regis- ter x and the value j in the immediate field, and stores the result in register x. operation: (a) (m(dp)) (x) (x)exor(j) j = 0 to 3 xamd j (exchange accumulator and memory data and decrement register y and skip) 0011011j 1 j 0 06 11 (y) = 15 grouping: ram to register transfer description: after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between regis- ter x and the value j in the immediate field, and stores the result in register x. subtracts 1 from the contents of register y. as a result of subtraction, when the con- tents of register y is 15, the next instruction is skipped. operation: (a) (m(dp)) (x) (x)exor(j) j = 0 to 3 (y) (y) ?1 c +j xami j (exchange accumulator and memory data and increment register y and skip) 0011010j 1 j 0 06 11 (y) = 0 grouping: ram to register transfer description: after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between regis- ter x and the value j in the immediate field, and stores the result in register x. adds 1 to the contents of register y. as a re- sult of addition, when the contents of register y is 0, the next instruction is skipped. operation: (a) (m(dp)) (x) (x)exor(j) j = 0 to 3 (y) (y) + 1 8 +j instruction code function mnemonic hexadecimal notation number of words number of cycles parameter type of instructions d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 44 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer (a) (b) (b) (a) (a) (y) (y) (a) (er 7 ?r 4 ) (b) (er 3 ?r 0 ) (a) (b) (er 7 ?r 4 ) (a) (er 3 ?r 0 ) (dr 2 ?r 0 ) (a 2 ? 0 ) (x) x, x = 0 to 3 (y) y, y = 0 to 15 (y) (y) + 1 (y) (y) ?1 (a) (m(dp)) (x) (x) exor(j) j = 0 to 3 (a) (m(dp)) (x) (x) exor(j) j = 0 to 3 (a) (m(dp)) (x) (x) exor(j) j = 0 to 3 (y) (y) ?1 (a) (m(dp)) (x) (x) exor(j) j = 0 to 3 (y) (y) + 1 tab tba tay tya teab tabe tda lxy x, y iny dey tam j xam j xamd j xami j register to register transfer 01 e 00 e 01 f 00 c 01 a 02 a 02 9 0c y +x 01 3 017 06 4 +j 06 j 06 c +j 06 8 +j 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ram addresses 000011110 000001110 000011111 000001100 000011010 000101010 000101001 011x 1 x 0 y 3 y 2 y 1 y 0 000010011 000010111 0011001j 1 j 0 0011000j 1 j 0 0011011j 1 j 0 0011010j 1 j 0 machine instructions (index by function) ram to register transfer skip condition detailed description carry flag cy mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 45 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer transfers the contents of register b to register a. transfers the contents of register a to register b. transfers the contents of register y to register a. transfers the contents of register a to register y. transfers the contents of registers a and b to register e. transfers the contents of register e to registers a and b. transfers the contents of register a to register d. loads the value x in the immediate field to register x, and the value y in the immediate field to register y. when the lxy instructions are continuously coded and executed, only the first lxy instruction is executed and other lxy instructions coded continuously are skipped. adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next instruction is skipped. subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. after transferring the contents of m(dp) to register a, an exclusive or operation is performed between register x and the value j in the immediate field, and stores the result in register x. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between register x and the value j in the immediate field, and stores the result in register x. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between register x and the value j in the immediate field, and stores the result in register x. subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between register x and the value j in the immediate field, and stores the result in register x. adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next instruction is skipped. continuous description (y) = 0 (y) = 15 (y) = 15 (y) = 0 instruction code function mnemonic hexadecimal notation number of words number of cycles parameter type of instructions d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 46 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer la n tabp p am amc a n sc rc szc cma rar lgop (a) n n = 0 to 15 (sk(sp)) (pc) (sp) (sp) + 1 (pc h ) p, p=0 to 7 (note) (pc l ) (dr 2 ?r 0 , a 3 ? 0 ) when urs=0, (b) (rom(pc)) 7 to 4 (a) (rom(pc)) 3 to 0 when urs=1, (cy) (rom(pc)) 8 (b) (rom(pc)) 7 to 4 (a) (rom(pc)) 3 to 0 (sp) (sp) ?1 (pc) (sk(sp)) (a) (a) + (m(dp)) (a) (a) + (m(dp))+ (cy) (cy) carry (a) (a) + n n = 0 to 15 (cy) 1 (cy) 0 (cy) = 0 ? (a) (a) cy a 3 a 2 a 1 a 0 logic operation instruction xor, or, and arithmetic operation 0b n 09 p 00 a 00 b 0a n 00 7 00 6 02 f 01 c 01 d 04 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 01011n 3 n 2 n 1 n 0 01001p 3 p 2 p 1 p 0 000001010 000001011 01010n 3 n 2 n 1 n 0 000000111 000000110 000101111 000011100 000011101 001000001 machine instructions (continued) note: p is 0 to 7 for m34282m1, p is 0 to 15 for m34282m2/e2. skip condition detailed description carry flag cy mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 47 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer continuous description overflow = 0 (cy) = 0 0/1 0/1 1 0 0/1 loads the value n in the immediate field to register a. when the la instructions are continuously coded and executed, only the first la instruction is executed and other la instructions coded continuously are skipped. transfers bits 7 to 4 to register b and bits 3 to 0 to register a when urs flag is cleared to ?.?these bits 7 to 0 are the rom pattern in address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) specified by registers a and d in page p. transfers bit 8 of rom pattern is transferred to flag cy when urs flag is set to ??(after the ursc instruction is executed). (one of stack is used when the tabp p instruction is executed.) adds the contents of m(dp) to register a. stores the result in register a. the contents of carry flag cy remains unchanged. adds the contents of m(dp) and carry flag cy to register a. stores the result in register a and carry flag cy. adds the value n in the immediate field to register a. the contents of carry flag cy remains unchanged. skips the next instruction when there is no overflow as the result of operation. sets (1) to carry flag cy. clears (0) to carry flag cy. skips the next instruction when the contents of carry flag cy is ?. stores the one? complement for register a? contents in register a. rotates 1 bit of the contents of register a including the contents of carry flag cy to the right. executes the logic operation selected by logic operation selection register lo between the contents of register a and register e, and stores the result in register a. instruction code function mnemonic hexadecimal notation number of words number of cycles parameter type of instructions d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 48 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer sb j rb j szb j seam sea n b a bl p, a ba a bla p, a (mj(dp)) 1 j = 0 to 3 (mj(dp)) 0 j = 0 to 3 (mj(dp)) = 0 ? j = 0 to 3 (a) = (m(dp)) ? (a) = n ? n = 0 to 15 (pc l ) a 6 ? 0 (pc h ) p (pc l ) a 6 ? 0 (note) (pc l ) (a 6 ? 4 , a 3 ? 0 ) (pc h ) p (pc l ) (a 6 ? 4 , a 3 ? 0 ) (note) 0010111j 1 j 0 0010011j 1 j 0 0001000j 1 j 0 000100110 000100101 01011n 3 n 2 n 1 n 0 11a 6 a 5 a 4 a 3 a 2 a 1 a 0 00011p 3 p 2 p 1 p 0 11a 6 a 5 a 4 a 3 a 2 a 1 a 0 000000001 11a 6 a 5 a 4 a 3 a 2 a 1 a 0 000010000 11a 6 a 5 a 4 p 3 p 2 p 1 p 0 05 c +j 04 c +j 02 j 02 6 02 5 0b n 18a +a 03 p 18 a +a 00 1 18 a +a 01 0 18 p +a 1 1 1 1 2 1 2 2 2 1 1 1 1 2 1 2 2 2 bit operation comparison operation note: p is 0 to 7 for m34282m1, p is 0 to 15 for m34282m2/e2. branch operation machine instructions (continued) skip condition detailed description carry flag cy mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 49 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer sets (1) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). clears (0) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of m(dp) is ?. skips the next instruction when the contents of register a is equal to the contents of m(dp). skips the next instruction when the contents of register a is equal to the value n in the immediate field. branch within a page : branches to address a in the identical page. branch out of a page : branches to address a in page p. branch within a page : branches to address (a 6 a 5 a 4 a 3 a 2 a 1 a 0 ) determined by replacing the low- order 4 bits of the address a in the identical page with register a. branch out of a page : branches to address (a 6 a 5 a 4 a 3 a 2 a 1 a 0 ) determined by replacing the low- order 4 bits of the address a in page p with register a. (mj(dp)) = 0 j = 0 to 3 (a) = (m(dp)) (a) = n n = 0 to 15 instruction code function mnemonic hexadecimal notation number of words number of cycles parameter type of instructions d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 50 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer bm a bml p, a bmla p, a rt rts t1ab tab1 tv1a snzt1 t2ab 1aa 07 p 1aa 05 0 1a p 04 4 04 5 047 057 05b 042 088 (sk(sp)) (pc) (sp) (sp) + 1 (pc h ) 2 (pc l ) a 6 ? 0 (sk(sp)) (pc) (sp) (sp) + 1 (pc h ) p (pc l ) a 6 ? 0 (note) (sk(sp)) (pc) (sp) (sp) + 1 (pc h ) p (pc l ) (a 6 ? 4 , a 3 ? 0 ) (note) (sp) (sp) ?1 (pc) (sk(sp)) (sp) (sp) ?1 (pc) (sk(sp)) at timer 1 stop (v1 0 =0) (r1 7 ?1 4 ) (b), (r1 3 ?1 0 ) (a) (t1 7 ?1 4 ) (b), (t1 3 ?1 0 ) (a) at timer 1 operating (v1 0 =1) (r1 7 ?1 4 ) (b), (r1 3 ?1 0 ) (a) (b) (t1 7 ?1 4 ) (a) (t1 3 ?1 0 ) (v1 2 ?1 0 ) (a 2 ? 0 ) (t1f) = 1 ? after skipping the next instruction (t1f) 0 (r2l 7 ?2l 4 ) (b) (r2l 3 ?2l 0 ) (a) (t2 7 ?2 4 ) (b), (t2 3 ?2 0 ) (a) 1 2 2 1 1 1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 10a 6 a 5 a 4 a 3 a 2 a 1 a 0 00111p 3 p 2 p 1 p 0 10a 6 a 5 a 4 a 3 a 2 a 1 a 0 001010000 10a 6 a 5 a 4 p 3 p 2 p 1 p 0 001000100 001000101 001000111 001010111 001011011 001000010 010001000 subroutine operation return operation machine instructions (continued) note : p is 0 to 7 for m34282m1, and p is 0 to 15 for m34282m2/e2. timer operation skip condition detailed description carry flag cy mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 51 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer skip at uncondition (t1f) = 1 call the subroutine in page 2 : calls the subroutine at address a in page 2. call the subroutine : calls the subroutine at address a in page p. call the subroutine : calls the subroutine at address (a 6 a 5 a 4 a 3 a 2 a 1 a 0 ) determined by replacing the low-order 4 bits of address a in page p with register a. returns from subroutine to the routine called the subroutine. returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. at timer 1 stop (v1 0 = 0), transfers the contents of register a and register b to timer 1 and reload register r1. at timer 1 operating (v1 0 = 1), transfers the contents of register a and register b to reload register r1. transfers the contents of timer 1 to registers a and b. transfers the contents of register a to registers v1. skips the next instruction when the contents of t1f flag is ?. after skipping, clears (0) to t1f flag. transfers the contents of register a and register b to timer 2 and reload register r2l. instruction code function mnemonic hexadecimal notation number of words number of cycles parameter type of instructions d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 52 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer machine instructions (continued) 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 carrier wave control operation tab2 tv2a snzt2 t2hab t2r2l scar rcar cld rd sd szd oea iae oga iag 001000000 001011010 001010010 010001001 001010011 010000111 010000110 000010001 000010100 000010101 000100100 000101011 010000100 001010110 010000000 000101000 040 05a 052 089 053 087 086 011 014 015 024 02b 084 056 080 028 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 (b) (t2 7 ?2 4 ), (a) (t2 3 ?2 0 ) (v2 3 ?2 0 ) (a 3 ? 0 ) (t2f) = 1 ? after skipping the next instruction (t2f) 0 (r2h 7 ?2h 4 ) (b) (r2h 3 ?2h 0 ) (a) (t2 7 ?2 4 ) (r2l 7 ?2l 4 ) (t2 3 ?2 0 ) (r2l 3 ?2l 0 ) (car) 1 (car) 0 (d) 0 (d(y)) 0 (y) = 0 to 7 (d(y)) 1 (y) = 0 to 7 (d(y)) = 0 ? (y) = 4 to 7 (e 1 , e 0 ) (a 1 , a 0 ) (a 2 ? 0 ) (e 2 ? 0 ) (g) (a) (a) (g) input/output operation timer operation skip condition detailed description carry flag cy mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 53 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer transfers the contents of timer 2 to registers a and b. transfers the contents of register a to registers v2. skips the next instruction when the contents of t2f flag is ?. after skipping, clears (0) to t2f flag. transfers the contents of register a and register b to reload register r2h. transfers the contents of reload register r2l to timer 2. sets (1) to port carr output flag (car). clears (0) to port carr output flag (car). clears (0) to port d (high-impedance state). clears (0) to a bit of port d specified by register y (high-impedance state). sets (1) to a bit of port d specified by register y. skips the next instruction when a bit of port d specified by register y is ?. outputs the contents of register a to port e. transfers the contents of port e to register a. outputs the contents of register a to port g. transfers the contents of port g to register a. (t2f) = 1 (d(y)) = 0 (y) = 4 to 7 instruction code function mnemonic hexadecimal notation number of words number of cycles parameter type of instructions d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 54 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer 000 00 d 00 3 05 9 05 8 08 2 08 f 08 e 00 f nop pof snzp cck tloa ursc tpu0a tpu1a wrst 000000000 000001101 000000011 001011001 001011000 010000010 010001111 010001110 000001111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (pc) (pc) + 1 ram back-up (p) = 1 ? stck changes to f(x in ) (lo 1 , lo 0 ) (a 1 , a 0 ) (urs) 1 (pu0 3 ?u0 0 ) (a 3 ? 0 ) (pu1 3 ?u1 0 ) (a 3 ? 0 ) (wdf1) 0 other operation skip condition detailed description carry flag cy mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 55 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer (p) = 1 no operation puts the system in ram back-up state. skips the next instruction when p flag is ?. after skipping, p flag remains unchanged. system clock (stck) changes to f(x in ) from f(x in )/8. execute this cck instruction at address 0 in page 0. transfers the contents of register a to the logic operation selection register lo. sets the most significant rom code reference enable flag (urs) to ?. transfers the contents of register a to register pu0. transfers the contents of register a to register pu1. initializes the watchdog timer flag (wdf1). mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 56 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer instruction code table d 3 d 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f xam 0 d 8 ? 4 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10000 11000 10111 11111 10?7 nop rc sc am amc tya tba bla cld iny rd sd dey teab cma rar tab tay szb 0 szb 1 szb 2 szb 3 sean seam tda tabe szc rt rts rb 0 rb 1 rb 2 rb 3 iae sb 0 sb 1 sb 2 sb 3 tabp 0 tabp 1 tabp 2 tabp 3 oea bm b bm b bm b bm b bm b bm b bm b bm b bm b bm b bm b bm b bm b bm b bm b bm b ba bl bl bl bl tab2 tv2a bmla xam 1 xam 2 xam 3 tam 0 tam 1 tam 2 tam 3 xami 0 xami 1 xami 2 xami 3 xamd 0 xamd 1 xamd 2 xamd 3 bml bml bml bml a 2 la 0 a 13 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 12 a 14 a 15 a 10 a 11 a 0 a 1 la 1 la 2 la 3 la 4 la 5 la 6 la 7 la 8 la 9 la 10 la 11 la 12 la 13 la 14 la 15 18?f lxy 0,0 lxy 1,0 lxy 2,0 lxy 0,1 lxy 1,1 lxy 2,1 lxy 0,2 lxy 1,2 lxy 2,2 lxy 0,3 lxy 1,3 lxy 2,3 lxy 0,4 lxy 1,4 lxy 2,4 lxy 0,5 lxy 1,5 lxy 2,5 lxy 0,6 lxy 1,6 lxy 2,6 lxy 0,7 lxy 1,7 lxy 2,7 snzp oga iag rcar pof lxy 3,0 lxy 3,1 lxy 3,2 lxy 3,3 lxy 3,4 lxy 3,5 lxy 3,6 lxy 3,7 cck tpu0a lxy 0,8 lxy 1,8 lxy 2,8 lxy 0,9 lxy 1,9 lxy 2,9 lxy 0,10 lxy 1,10 lxy 2,10 lxy 011 lxy 1,11 lxy 2,11 lxy 0,12 lxy 1,12 lxy 2,12 lxy 0,13 lxy 1,13 lxy 2,13 lxy 0,14 lxy 1,14 lxy 2,14 lxy 0,15 lxy 1,15 lxy 2,15 lxy 3,8 lxy 3,9 lxy 3,10 lxy 3,11 lxy 3,12 lxy 3,13 lxy 3,14 lxy 3,15 tabp 4 tabp 5 tabp 6 tabp 7 bl bl bl bl bml bml bml bml lgop szd snzt1 tv1a wrst bl bml bla bmla sea 1 1 a a a a a a a 1 0 a a a a a a a 1 1 a a a p p p p 1 0 a a a p p p p 0 1 0 1 1 n n n n ba 1 1 a a a a a a a 0 0 0 1 0 1 0 1 1 szd tloa t1ab tab1 ursc hex. notation the above table shows the relationship between machine language codes and machine language instructions. d 3 ? 0 show the low-order 4 bits of the machine language code, and d 8 ? 4 show the high-order 5 bits of the machine language code. the hexadecimal representation of the code is also provided. there are one-word instructions and two-word instructions, but only the first word of each instruction is shown. do not use the code marked . the codes for the second word of a two-word instruction are described below. the second word bl* bl* bl* bl* bl* bl* bl* bl* snzt2 t2r2l bml* bml* bml* bml* bml* bml* bml* bml* tpu1a scar t2ab t2hab tabp 8* tabp 9* tabp 10* tabp 11* tabp 12* tabp 13* tabp 14* tabp 15* * cannot be used in the m34282m1. mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 57 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer register structure v1 2 v1 1 v1 0 timer control register v1 auto-control output by timer 1 is invalid auto-control output by timer 1 is valid carrier wave output (carry) bit 5 of watchdog timer (wdt) stop (timer 1 state retained) operating 0 1 0 1 0 1 carrier wave output auto-control bit timer 1 count source selection bit timer 1 control bit at reset : 000 2 w at ram back-up : 000 2 v1 3 v1 2 v1 1 v1 0 timer control register v1 to expand ??interval is invalid to expand ??interval is valid (when v2 2 =1 selected) carrier wave generation function invalid carrier wave generation function valid f(x in ) f(x in )/2 stop (timer 2 state retained) operating 0 1 0 1 0 1 0 1 carrier wave ??interval expansion bit carrier wave generation function control bit timer 2 count source selection bit timer 2 control bit at reset : 0000 2 w at ram back-up : 0000 2 at reset : 00 2 at ram back-up : 00 2 w l o 1 0 0 1 1 l o 0 0 1 0 1 lo 1 lo 0 logic operation selection bits logic operation selection register lo logic operation function exclusive logic or operation (xor) or operation (or) and operation (and) not available pu0 3 pu0 2 pu0 1 pu0 0 pull-down transistor off, key-on wakeup invalid pull-down transistor on, key-on wakeup valid pull-down transistor off, key-on wakeup invalid pull-down transistor on, key-on wakeup valid pull-down transistor off, key-on wakeup invalid pull-down transistor on, key-on wakeup valid pull-down transistor off, key-on wakeup invalid pull-down transistor on, key-on wakeup valid ports g 2 , g 3 pull-down transistor control bit ports g 0 , g 1 pull-down transistor control bit port e 1 pull-down transistor control bit port e 0 pull-down transistor control bit pull-down control register pu0 at reset : 0000 2 at ram back-up : state retained w 0 1 0 1 0 1 0 1 pu1 3 pu1 2 pu1 1 pu1 0 pull-down transistor off, key-on wakeup invalid pull-down transistor on, key-on wakeup valid pull-down transistor off, key-on wakeup invalid pull-down transistor on, key-on wakeup valid pull-down transistor off, key-on wakeup invalid pull-down transistor on, key-on wakeup valid pull-down transistor off, key-on wakeup invalid pull-down transistor on, key-on wakeup valid port d 7 pull-down transistor control bit port d 6 pull-down transistor control bit port d 5 pull-down transistor control bit port d 4 pull-down transistor control bit pull-down control register pu1 at reset : 0000 2 at ram back-up : state retained w 0 1 0 1 0 1 0 1 mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 58 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer absolute maximum ratings parameter supply voltage input voltage output voltage power dissipation operating temperature range storage temperature range conditions ta = 25 c unit v v v m w c c ratings ?.3 to 5 ?.3 to v dd +0.3 ?.3 to v dd +0.3 300 ?0 to 85 ?0 to 125 symbol v dd v i v o p d t opr t stg recommended operating conditions (ta = ?0 c to 85 c, v dd = 1.8 v to 3.6 v, unless otherwise noted) parameter supply voltage ram back-up voltage (at ram back-up mode) supply voltage ??level input voltage ports d 4 ? 7 , e, g ??level input voltage x in ??level input voltage ports d 4 ? 7 , e, g ??level input voltage x in ??level peak output current ports d, e 1 , g ??level peak output current port e 0 ??level peak output current carr ??level peak output current carr ??level average output current ports d, e 1 , g ??level average output current port e 0 ??level average output current carr ??level average output current carr system clock frequency voltage drop detection circuit detection voltage voltage drop detection circuit low voltage determination time power-on reset circuit valid power source rising time limits max. 3.6 3.6 v dd v dd 0.2v dd 0.2v dd ? ?4 ?0 4 ? ?2 ?0 2 4 500 1.80 1.56 1.2 1 typ. 0 1.50 0.2 min. 1.8 1.1 0.7v dd 0.8v dd 0 0 1.10 1.40 symbol v dd v ram v ss v ih v ih v il v il i oh (peak) i oh (peak) i oh (peak) i ol (peak) i oh (avg) i oh (avg) i oh (avg) i ol (avg) f(x in ) v det t det t pon unit v v v v v v v ma ma ma ma ma ma ma ma mhz khz v ms ms when stck = f(x in )/8 selected when stck = f(x in ) selected note: the average output current ratings are the average current value during 100 ms. conditions v dd = 3.0 v v dd = 3.0 v v dd = 3.0 v v dd = 3.0 v v dd = 3.0 v v dd = 3.0 v v dd = 3.0 v v dd = 3.0 v v dd = 3.0 v v dd = 3.0 v v dd = 3.0 v v dd = 3.0 v ceramic resonance ceramic resonance ta=25 c when supply voltage passes the detected voltage at 50v/s. v dd = 0 to 2.2 v mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 59 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer parameter ??level output voltage port carr ??level output voltage x out ??level output voltage ports d, e 1 , g ??level output voltage port e 0 ??level output voltage carr ??level output voltage x out ??level input current ports d 4 ? 7 , e, g ??level input current ports e 0 , e 1 output current at off-state ports d, e 0 , e 1 , g supply current (when operating) supply current (at ram back-up) pull-down resistor value ports d 4 ? 7 , e, g feedback resistor value between x in ? out test conditions i ol = 2 ma i ol = 0.2 ma i oh = ? ma i oh = ?2 ma i oh = ?0 ma i oh = ?.2 ma v i = v ss v i = v dd pull-down transistor in off-state v o = v ss f(x in ) = 4.0 mhz f(x in ) = 500 khz ta = 25 c v dd = 3 v, v i = 3 v limits symbol v ol v ol v oh v oh v oh v oh i il i ih i oz i dd r ph r osc unit v v v v v v a a a a a a a k ? k ? max. 0.9 0.9 ? 1 ? 800 500 3 0.5 300 3200 typ. min. 2.1 1.5 1.0 2.1 75 700 electrical characteristics (ta = ?0 c to 85 c, v dd = 3 v, unless otherwise noted) basic timing diagram system clock ports d, e, g output ports d, e, g input stck parameter pin name machine cycle mi mi+1 d 0 d 7 ,e 0 ,e 1 g 0 g 3 d 4 d 7 e 0 e 2 g 0 g 3 400 250 1 0.1 150 mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 60 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer table 10 product of built-in prom version prom size ( ? 9 bits) 2048 words ram size ( ? 4 bits) 64 words product m34282e2gp rom type one time prom [shipped in blank] package 20p2e/f-a built-in prom version in addition to the mask rom versions, the 4282 group has the one time prom versions whose proms can only be written to and not be erased. the built-in prom version has functions similar to those of the mask rom versions, but it has prom mode that enables writing to built-in prom. table 10 shows the product of built-in prom version. figure 27 and 28 show the pin configurations of built-in prom versions. the one time prom version has pin-compatibility with the mask rom version. fig. 27 pin configuration of built-in prom version pin configuration (top view) v ss 2 3 4 5 6 7 8 9 10 1 19 18 17 16 15 14 13 12 11 20 d 7 d 2 d 3 d 4 d 5 d 1 d 0 carr v dd d 6 e 2 g 3 g 2 e 0 e 1 x in x out g 0 g 1 m34282e2gp outline 20p2e/f-a mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 61 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer (1) prom mode (serial input/output) the m34282e2gp has a prom mode in addition to a normal operation mode. it has a function to serially input/output the command codes, addresses, and data required for operation (e.g., read and program) on the built-in prom using only a few pins. this mode can be selected by setting pins sda (serial data input/output), sclk (serial clock input), pgm and v pp to h after connecting wires as shown in figure 28 and powering on the v dd pin, and then applying 12.5v to the v pp pin. in the prom mode, three types of software commands (read, program, and program verify) can be used. clock-synchronous serial i/o is used, beginning from the lsb (lsb first). rrefer to the mitsubishi microcomputer development support tools hompage (http://www.tool-spt.mesc.co.jp/index_e.htm). about the serial programmer for the mitsubishi single-chip microcomputers. fig. 28 pin configuration of built-in prom version (continued) pin configuration (top view) sda sclk pgm vpp vss v dd * d 0 d 1 d 2 d 3 v dd carr d 7 d 6 d 5 d 4 2 3 4 5 6 7 8 9 10 1 19 18 17 16 15 14 13 12 11 20 v ss e 0 g 1 g 2 g 3 g 0 e 1 x in x out e 2 m34282e2gp * : connected to the ceramic resonance circuit. note: the state of disconnected pins are the same as that at reset. outline 20p2e/f-a mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 62 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer number of transfer in the first transfer, the command code is input. then, address input or data input/output is performed according to the contents of the command code. table 11 shows the software command used in the prom mode. the following explains each software command. (2) functional outline in the prom mode, data is transferred with the clock- synchronous serial input/output. the input data is read through the sda pin into the internal circuit synchronously with the rising edge of the serial clock pulse. the output data is output from the sda pin synchronously with the falling edge of the serial clock pulse. data is transferred in units of 8 bits. table 11 software command command read program program verify first command code input 15 16 25 16 35 16 second read address l (input) program address l (input) program address l (input) fourth read data l (output) program data l (input) program data l (input) third read address h (input) program address h (input) program address h (input) number of transfer command read program program verify fifth read data h (output) program data h (input) program data h (input) seventh verify data h (output) sixth verify data l (output) (3) read input the command code 15 16 in the first transfer. proceed and input the low-order 8 bits and the high-order 8 bits of the address and pull the pgm pin to l. when this is done, the contents of input address is read and stored into the internal data latch. when the pgm pin is released back to h and serial clock is input to the sclk pin, the low-order 8 bits and high-order 8 bits of read data which have been stored into the data latch, are serially output from the sda pin. note: when outputting the read data, the sda pin is switched for output at the first falling of the serial clock. the sda pin i s placed in the high-impedance state during the th (c e) period after the last rising edge of the serial clock (at the 16th bit). fig. 29 timing at reading t cr t rc 10101000 a0 a7 command code input (15 16 ) read address input (l) read address input (h) sclk sda pgm read t wr t ch d0 d7 read data output (l) t ch d8 read data output (h) t ch 0000000 a8a9 00000 a10 mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 63 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer fig. 31 timing at program verifying and pull the pgm pin to l. when this is done, the program data is programmed to the specified address. (4) program input command code 25 16 in the first transfer. proceed and input the low-order 8 bits and high-order 8 bits of the address and the low-order 8 bits and high-order 8 bits of program data, fig. 30 timing at programming (5) program verify input command code 35 16 in the first transfer. proceed and input the low-order 8 bits and high-order 8 bits of the address and the low-order 8 bits and high-order 8 bits of program data, and pull the pgm pin to l. when this is done, the program data is programmed to the specified address. then, when the pgm pin is pulled to l again after it is released back to h, the address programmed with the program command is read and verified and stored into the internal data latch. when the pgm pin is released back to h and serial clock is input to the sclk pin, the verify data that has been stored into the data latch is serially output from the sda pin. note: when outputting the verify data, the sda pin is switched for output at the first falling of the serial clock. the sda pin is placed in the high-impedance state during the th (c e) period after the last rising edge of the serial clock (at the 16th bit). 10100100 a0 a7 commanf code input (25 16 ) program address input (l) program address input (h) sclk sda pgm program t ch d0 d7 program data input (l) t cp t wp t ch d8 program data input (h) t ch 0000000 t ch a8a9 00000 a10 10101100 a0 a7 command code input (35 16 ) program address input (l) program address input (h) sclk sda pgm t ch d0 d7 program data input (l) t cp t wp t ch d8 program data input (h) t ch 0000000 t ch a8 a9 00000 program t cr t rc sclk sda pgm verify t wr d0 d7 verify data output (l) d8 verify data output (h) t ch 0000000 a10 mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 64 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer program algorithm flow chart start v dd = 4v,v pp = 12.5v adrs = first location x=0 write program data x = x + 1 program one pulse of 0.2ms x = 25? verify byte? yes no fail pass last adrs? no yes read command device passed verify byte? pass fail device failed inc adrs 35 16 din write program-verify command verify all byte? fail pass 15 16 program pulse of 0.2xms duration write program command 25 16 write program data din v dd = 4v,v pp = 4v mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 65 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer timing requirement condition and switching characteristics (ta = 25 c, v dd = 4.0 v, v pp = 12.5 v) max. 0.21 5.25 180 timing diagram symbol t ch t cr t wr t rc t cp t wp t owp t c(ck) t w(ckh) t w(ckl) t r(ck) t f(ck) t d(c q) t h(c q) t h(c e) t su(d c) t h(c d) parameter serial transfer width time read wait time after transfer read pulse width transfer wait time after read program wait time after transfer program pulse width added program pulse width sclk input cycle time sclk h pulse width sclk l pulse width sclk rising time sclk falling time sda output delay time sda output hold time sda output hold time (only for 16th bit) sda input set-up time sda input hold time unit s s ns s s ms ms s ns ns ns ns ns ns ns ns ns min. 2.0 2.0 500 2.0 2.0 0.19 0.19 1.0 450 450 40 40 0 0 100 60 180 limits t c(ck) t w(ckh) t w(ckl) t d(c-q) t h(c-e) t f(ck) t r(ck) t su(d-c) t h(c-d) sclk sda output sda input t h(c-q) measurement condition output timing voltage: vol = 0.8 v, voh = 2.0 v input timing voltage: vil = 0.2 vd d, vih = 0.8 vdd mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 66 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer fig. 32 flow of writing and test of the product shipped in blank (6) notes on handling ? a high-voltage is used for writing. take care that overvoltage is not applied. take care especially at turning on the power. ? for the one time prom version, mitsubishi electric corp. does not perform prom writing test and screening in the assembly process and following processes. in order to improve reliability after writing, performing writing and test according to the flow shown in figure 32 before using is recommended. writing with prom programmer screening (leave at 150 c for 40 hours) (note) verify test with prom programmer function test in target device since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 c exceeding 100 hours. note: mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 67 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer package outline ssop20-p-225-0.65 weight(g) jedec code 0.08 eiaj package code lead material alloy 42/cu alloy 20p2e/f-a plastic 20pin 225mil ssop symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h e a 1 i 2 .17 0 0 .13 0 .4 6 .3 4 .2 6 .3 0 .0 1 .1 0 .15 1 .22 0 .15 0 .5 6 .4 4 .65 0 .4 6 .5 0 .0 1 .8 5 .2 0 .45 1 .32 0 .2 0 .6 6 .5 4 .6 6 .7 0 .1 0 b 2 .35 0 0 10 e e 1 20 11 10 1 h e e d e y f a a 2 a 1 l 1 l c e b 2 e 1 i 2 recommended mount pad detail f x z 1 0.325 0.475 0.13 z g b x m detail g z z 1 mitsubishi electric preliminar y notice: this is not a final specification. some parametric limits are subject to change. 68 mitsubishi microcomputers 4282 group single-chip 4-bit cmos microcomputer customers parts number note: the fonts and size of characters are standard mitsubishi type. mitsubishi ic catalog name and mitsubishi lot number mitsubishi ic catalog name and mitsubishi lot number notes 1 : the mark field should be written right aligned. 2 : the fonts and size of characters are standard mitsubishi type. 3 : customers parts number can be up to 4 characters: only 0 to 9, a to z, +, -, /, (, ), &, ?, . (period), and , (comma) are usable. 20p2e/f-a (20-pin ssop) mark specification form mitsubishi ic catalog name please choose one of the marking types below (a, b), and enter the mitsubishi ic catalog name and the special mark (if needed). a. standard mitsubishi mark b. customers parts number + mitsubishi ic catalog name mitsubishi ic catalog name mitsubishi ic catalog name 20 11 10 1 mitsubishi lot number (4-digit or 5-digit) 20 11 10 1 mitsubishi lot number (4-digit or 5-digit) rom number (3-digit) ? 2000 mitsubishi electric corp. new publication, effective june. 2000. specifications subject to change without notice. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product be st suited to the customer s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers co ntact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used unde r circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a pro duct contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these ma terials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licens e from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detail s on these materials or the products contained therein. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making y our circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. single-chip 4-bit cmos microcomputer 4282 group mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. rev. rev. no. date 1.0 first edition 000619 revision description list 4282 group data sheet (1/1) revision description |
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